A 40-Gb - Jri Lee (IEEE Journal of solid state circuits)
A phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly spaced points, providing half-quadrature phases. The phase detector employs eight flip-flops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs. Fabricated in 0.18-μm CMOS technology, the circuit produces a clock jitter of 0.9 psrms and 9.67 pspp with a PRBS of 231-1 while consuming 144 mW from a 2-V supply.