40-43-Gb/s OC-768 16 1 MUX - Hai Tao
In this paper, we present two copackaged ICs that provide complete OC-768 16:1 multiplexer (MUX) and clock multiplying unit (CMU) functionality. The 17-input 2.5-2.68-Gb/s parallel interface is Serdes Framer Interface Level 5 (SFI-5) compliant while the 40-43-Gb/s output satisfies OC-768 jitter generation specifications with 7 dB of margin. The system architecture and two-chip partitioning are discussed, followed by descriptions of the design challenges including SFI-5 compliance, 40-Gb/s MUX timing, and 20-GHz clock generation. A novel technique for stabilizing timing margins in the final high-speed multiplexer stage using in-phase and quadrature clocks is also presented. This chipset accommodates 11 bits of static skew and 21 bits of dynamic wander at the SFI-5 interface, while generating 125 fs rms of random jitter and 3.1 ps peak-to-peak of deterministic jitter at its 40-43-Gb/s outputs. The measured bit-error ratio is less than 10-15 for 231-1 PRBS data and is measurement time limited. The two chips occupy 15.6 mm2 and 8.25 mm2 of die area. Both are implemented in a 120-GHz fT SiGe BiCMOS process.
Keywords: 16:1 multiplexer; 17-input 2.5-2.68-Gb/s parallel interface; 20-GHz clock generation; 40 to 43 Gbit/s.; 40-Gb/s MUX timing; OC-768 16:1 MUX/CMU chipset; OC-768 jitter generation specifications; PRBS data; SFI-5 compliance; SFI-5 interface; SONET; Serdes Framer Interface Level 5 compliance; SiGe BiCMOS process; Bit-error ratio; Chipset accommodates; Clock multiplying unit functionality; Delay-locked loop; Deterministic jitter; Dynamic wander; High-speed multiplexer stage; Optical networking; Optical transmission; Peak-to-peak.; Phase noise; Phase-locked loop; Quadrature clocks; Random jitter; Static skew; System architecture; Timing margin stabilization; Two-chip partitioning