40-43-Gb/s OC-768 16 1 MUX

In this paper, we present two copackaged ICs that provide complete OC-768 16:1 multiplexer (MUX) and clock multiplying unit (CMU) functionality. The 17-input 2.5-2.68-Gb/s parallel interface is Serdes Framer Interface Level 5 (SFI-5) compliant while the 40-43-Gb/s output satisfies OC-768 jitter gene...

詳細記述

書誌詳細
出版年:	IEEE Journal of solid state circuits 38, 12 (2003).
第一著者:	Hai Tao
フォーマット:	論文
言語:	English
主題:	16:1 multiplexer. 17-input 2.5-2.68-Gb/s parallel interface. 20-GHz clock generation. 40 to 43 Gbit/s. 40-Gb/s MUX timing. OC-768 16:1 MUX/CMU chipset. OC-768 jitter generation specifications. PRBS data. SFI-5 compliance. SFI-5 interface. SONET. Serdes Framer Interface Level 5 compliance. SiGe BiCMOS process. Bit-error ratio. Chipset accommodates. Clock multiplying unit functionality. Delay-locked loop. Deterministic jitter. Dynamic wander. High-speed multiplexer stage. Optical networking. Optical transmission. Peak-to-peak. Phase noise. Phase-locked loop. Quadrature clocks. Random jitter. Static skew. System architecture. Timing margin stabilization. Two-chip partitioning.