Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM - Zerbe, J.L.
A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10-15 and power equal to 40 mW/Gb/s has been measured when operating over a 20-in backplane with two connectors at 10 Gb/s.
Keywords: 2.5 to 10 Gbit/s.; 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell; 40 mW; SerDes; Adaptive equalizers; Backplane environment; Bit-error rate; Decision feedback equalizers; Equalization; Flexible 2-PAM/4-PAM clock data recovery circuit; Folded multitap transmitter equalizer; Multilevel systems; Multitap receiver equalizer; Pulse amplitude modulation; Receive clock recovery; Select transitions; Serial links