Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM

A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10-15 and power equal to...

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Podrobná bibliografie
Vydáno v:IEEE Journal of solid state circuits 38, 12 (2003).
Hlavní autor: Zerbe, J.L
Médium: Článek
Jazyk:English
Témata:
2.5 to 10 Gbit/s.
2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell.
40 mW.
SerDes.
Adaptive equalizers.
Backplane environment.
Bit-error rate.
Decision feedback equalizers.
Equalization.
Flexible 2-PAM/4-PAM clock data recovery circuit.
Folded multitap transmitter equalizer.
Multilevel systems.
Multitap receiver equalizer.
Pulse amplitude modulation.
Receive clock recovery.
Select transitions.
Serial links.