Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM
A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10-15 and power equal to...
| Τόπος έκδοσης: | IEEE Journal of solid state circuits 38, 12 (2003). |
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| Κύριος συγγραφέας: | |
| Μορφή: | Άρθρο |
| Γλώσσα: | English |
| Θέματα: |