00000cab a22000003a 4500 UP-99796217609277659 Buklod 20231007234126.0 m |o d | ta 100507s xx d | ||r ||||| || DENGII eng Casper, B. An 8-Gb s simultaneous bidirectional link with on-die waveform capture. pp. 2111-2120 A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-μm CMOS. This equalized transceiver has been optimized for small area (329 μm × 395 μm) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding bandwidth overhead and reduce latency, jitter, and complexity. This link is self-configuring through the use of automatic comparator offset trim and adaptive deskew. Comprehensive diagnostic capabilities have been integrated into the transceiver to provide link, interconnect, and circuit characterization without the use of external test equipment. With a resolution of 4 mV and 9 ps, these capabilities enable on-die eye diagram generation, equivalent time waveform capture, noise characterization, and jitter distribution measurements 0.18 micron. 158 mW. 329 micron. 395 micron. 4 mV 9 ps resolution. 8 Gbit/s. 8-Gb/s simultaneous bidirectional link. Adaptive deskew. Automatic comparator offset trim. Circuit characterization. Coding bandwidth overhead elimination. Complexity reduction. Comprehensive diagnostic capabilities. Equalized transceiver. Full-duplex transceiver. High-speed I/O. Interconnect. Jitter distribution measurements. Jitter reduction. Latency reduction. Noise characterization. On-die eye diagram generation. On-die oscilloscope. On-die waveform capture. Per-pin skew compensation. Point-to-point parallel links. Preemphasis. Self-configuration. Self-testing. Source-synchronous clocking. Time waveform capture. 0.18 μm CMOS. IEEE Journal of solid state circuits 38, 12 (2003). FO Article