An 8-Gb - Casper, B. (IEEE Journal of solid state circuits)
A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-μm CMOS. This equalized transceiver has been optimized for small area (329 μm × 395 μm) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding bandwidth overhead and reduce latency, jitter, and complexity. This link is self-configuring through the use of automatic comparator offset trim and adaptive deskew. Comprehensive diagnostic capabilities have been integrated into the transceiver to provide link, interconnect, and circuit characterization without the use of external test equipment. With a resolution of 4 mV and 9 ps, these capabilities enable on-die eye diagram generation, equivalent time waveform capture, noise characterization, and jitter distribution measurements