An 8-Gb
A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-μm CMOS. This equalized transceiver has been optimized for small area (329 μm × 395 μm) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding b...
| Publicat a: | IEEE Journal of solid state circuits 38, 12 (2003). |
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| Autor principal: | |
| Format: | Article |
| Idioma: | English |
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