A second-order semidigital clock recovery circuit based on injection locking.

A second-order semidigital clock recovery circuit based on injection locking.

A compact (1 mm × 160 μm) and low-power (80-mW) 0.18-μm CMOS 3.125-Gb/s clock and data recovery circuit is described. The circuit utilizes injection locking to filter out high-frequency reference clock jitter and multiplying delay-locked loop duty-cycle distortions. The injection-locked slave oscill...

詳細記述

書誌詳細
出版年:IEEE Journal of solid state circuits 38, 12 (2003).
第一著者: Hiok-Tiaq Ng
フォーマット: 論文
言語:English
主題:
1 mm.
CMOS clock.
Clock multiplication.
Current steering.
Data recovery circuit.
Delay-locked loop duty-cycle distortion multiplication.
Frequency acquisition.
Frequency offset tracking.
Frequency tracking.
High-frequency reference clock jitter filtering.
High-speed transceivers.
Injection locking.
Injection-locked slave oscillator output.
Multiplying delay-locked loop.
Output clock interpolation.
Phase interpolation.
Phase wander.
Second-order semidigital clock recovery circuit.