TY  - THES
T1  - Built-in self-test implementation on ARM7TDM-S microprocessor
A1  - Esguerra, Ralph Joseph A.
A2  - Marimla, Josef Ronald A.
A2  - Retirado, Aga Nasser E.
LA  - English
UL  - https://tuklas.up.edu.ph/Record/UP-99796217609277649
AB  - The total cost of integrated chips is composed of the design cost, production cost, and testing cost. As integrated chips increase in complexity, testing through automatic test equipment (ATE) becomes very expensive and time-consuming. Built-in self-test (BIST) primarily addresses these problems. This is an additional functionality that allows the system to test itself. Since BIST is incorporated with the chip, chips can be tested simultaneously. The BIST introduces an initial testing process for the chips. This possibly may decrease the chips that will undergo ATE testing, which results in decreased costs and time for testing.  The objective of the project is to implement BIST on the ARM7TDM-S microprocessor. The project involves implementing the STUMPS partial scan-based BIST on the system. Registers from different blocks in the processor will be transformed into scan registers where test inputs and test outputs are shifted in and shifted out respectively. Though partial scan-based BIST presents high testing time, it minimizes area overhead and assures high fault coverage.  Costs for the addition of BIST to the system will be quantified in term of its deviation from the original system with respect to area, speed, and average power.  The project was coded using Verilog HDL, simulated using Synopsis® VCS, and synthesized using 90-nanometer standard cells. Its layout was generated by Synopsys® Astro. Compared to the base core, it has a decrease in maximum operating frequency of 11.85%, an overhead of 17.42% and an increase of 26.1% in average power consumption.
CN  - LG 993.5 2010 E64 E84
KW  - Integrated circuits : Testing.
KW  - Microprocessors : Testing.
KW  - ARM7TDM-S microprocessor.
ER  -