Impact of capacitor dielectric relaxation on a 14-bit 70-MS

In this paper, phenomena of charge absorption and relaxation in the plasma enhanced chemical vapor deposition (PECVD) silicon nitride dielectric (Si3N4) used in the capacitors of a 45-GHz fT, 0.4-μm Lmin SiGe BiCMOS are observed and interpreted. When such capacitors are used to design a pipelined 14...

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Manylion Llyfryddiaeth
Cyhoeddwyd yn:	IEEE Journal of solid state circuits 38, 12 (2003).
Prif Awdur:	Zanchi, A.
Fformat:	Erthygl
Iaith:	English
Pynciau:	1 W. 1-MHz input. 11.7-bit ENOB. 14-bit 70-MS/s pipeline ADC. 3-V BiCMOS. 3.3 V. 5.3 mm. 72.5-dBFS SNR. 8-LSB-wide gaps. 82-dBc SFDR. ADC test chip. LPCVD oxide capacitors. Matlab behavioral simulations. PECVD. SPICE circuit simulations. Ad-hoc experimental tests. Analog-to-digital converter. Capacitor dielectric relaxation. Charge absorption. Charge relaxation. Converter performance. Integral nonlinearity. Low frequencies. Low-density low-pressure chemical vapor deposition. Pipelined 14-bit 70-MS/s switched-capacitor. Pipelined architecture. Plasma enhanced chemical vapor deposition. Residual charge. Silicon nitride dielectric. Silicon-germanium BiCMOS. Switched-capacitor circuits. 45-GHz fT 0.4-μm Lmin SiGe BiCMOS. Si3N4. SiO2.