A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000

A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000

Time jitter in continuous-time ΣΔ modulators is a known limitation on the maximum achievable signal-to-noise-ratio (SNR). Analysis of time jitter in this type of converter shows that a switched-capacitor (SC) feedback digital-to-analog converter (DAC) reduces the sensitivity to time jitter significa...

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Podrobná bibliografie
Vydáno v:IEEE Journal of solid state circuits 38, 12 (2003).
Hlavní autor: Van Veldhoven, R.H.M
Médium: Článek
Jazyk:English
Témata:
3G mobile communication.
Capacitors.
Code division multiple access.
Digital-analogue conversion.
Jitter.
Phase locked loops.
Phase locked oscillators.
Radio receivers.
Sigma-delta modulation.
Transceivers.