A 69-mW 10-bit 80-MSample - Byung-Moo Min
A 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing wide-bandwidth telescopic amplifier and an early comparison technique with a constant delay circuit have been developed to further reduce power consumption. The ADC is implemented in a 0.18-μm dual-gate-oxidation CMOS process technology, achieves 72.8-dBc spurious free dynamic range, 57.92-dBc signal-to-noise ratio, 9.29 effective number of bits (ENOB) for a 99-MHz input at full sampling rate, and consumes 69 mW from a 3-V supply. The ADC occupies 1.85 mm2.
Keywords: 0.18-/zm dual-gate-oxidation CMOS process technology; 10 bit; 10-bit ADC; 10-bit pipeline; 3-V supply; 57.92-dBc signal-to-noise ratio; 69 mW; 69-mW ADC; 72.8-dBc spurious free dynamic range; 80-MSample/s ADC; 9.29 effective number of bits; 99-MHz input; Pipelined CMOS ADC; Amplifier sharing technique; Analog-to-digital converter; Area-efficient architecture; Constant delay circuit; Consumes 69 mW; Early comparison scheme; Feedback signal polarity inverting technique; Full sampling rate; Low-power pipelined analog-to-digital conversion; Opamp sharing technique; Pipeline stages; Power consumption reduction; Power-efficient architecture; Sample-and-hold block; Wide-swing wide-bandwidth telescopic amplifier