A 69-mW 10-bit 80-MSample

A 69-mW 10-bit 80-MSample

A 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal...

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书目详细资料
发表在:IEEE Journal of solid state circuits 38, 12 (2003).
主要作者: Byung-Moo Min
格式: 文件
语言:English
主题:
0.18-/zm dual-gate-oxidation CMOS process technology.
10 bit.
10-bit ADC.
10-bit pipeline.
3-V supply.
57.92-dBc signal-to-noise ratio.
69 mW.
69-mW ADC.
72.8-dBc spurious free dynamic range.
80-MSample/s ADC.
9.29 effective number of bits.
99-MHz input.
Pipelined CMOS ADC.
Amplifier sharing technique.
Analog-to-digital converter.
Area-efficient architecture.
Constant delay circuit.
Consumes 69 mW.
Early comparison scheme.
Feedback signal polarity inverting technique.
Full sampling rate.
Low-power pipelined analog-to-digital conversion.
Opamp sharing technique.
Pipeline stages.
Power consumption reduction.
Power-efficient architecture.
Sample-and-hold block.
Wide-swing wide-bandwidth telescopic amplifier.