50-Gb/s 4-b multiplexer - Sano, K.
A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-Vpp output amplitude, and the DEMUX exhibited >180° phase margin from 4 to 50 Gb/s for 231-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 231-1 PRBS was confirmed with the packaged MUX and DEMUX.
Keywords: 4 bit; 4 to 50 Gbit/s.; InP; InP HEMT IC; Multiplexer/demultiplexer chip set; Pseudorandom bit sequence; Timing design