STS-768 multiplexer with full-rate output data retimer in InP HBT.

A 16:1 STS-768 multiplexer IC has been designed and fabricated using the Vitesse Semiconductor VIP-1 process. This IC is part of a complete chip-set solution for a 40-Gb/s STS-768 optical communication transceiver module. The multiplexer IC features a full-rate clock multiplication unit and a data r...

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发表在:	IEEE Journal of solid state circuits 38, 9 (2003).
主要作者:	Hendarman, A.
格式:	文件
语言:	English
主题:	3.6 V. 5.2 V. 3.6 W. 40 GHz. 40 Gbit/s. InP. InP HBT IC. STS-768 multiplexer. STS-768 multiplexer IC. Vitesse Semiconductor VIP-1 process. Clock multiplication unit. Clock tree. Current-mode logic gate circuit. Duty cycle distortion. Eye quality. Frequency divider. Full-rate data retimer. Layout design. Optical communication transceiver module. Output driver. Package design. Phase locked loop. Timing jitter. Voltage controlled oscillator.