A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator.

A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator.

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass ΣΔ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations,...

詳細記述

書誌詳細
出版年:IEEE Journal of solid state circuits 38, 8 (2003).
第一著者: Gerfers, F.
フォーマット: 論文
言語:English
主題:
0.5 micron.
1.5 V.
12 bit.
135 muW.
25 kHz.
3.3 V.
CMOS.
Active RC integrators.
Analog-to-digital converter.
Circuit nonidealities.
Continuous-time loop filter.
Dynamic range.
Low supply voltage.
Peak signal-to-noise-plus-distortion ratio.
Performance limitations.
Power consumption.
Threshold voltages.
Continuous-time third-order ΣΔ modulator.