TY  - JOUR
T1  - A 500-Mb
JF  - IEEE Journal of solid state circuits
A1  - Engling Yeo
LA  - English
UL  - https://tuklas.up.edu.ph/Record/UP-99796217609277412
AB  - Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-μm CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhead. The survivor-path decoding logic of a conventional Viterbi decoder register exchange is adapted to detect the two most likely paths. The 4-mm2 chip has been verified to decode at 500 Mb/s with 1.8-V supply. These decoders can be used as constituent decoders for Turbo codes in high-performance applications requiring information rates that are very close to the Shannon limit.
KW  - 0.18 micron.
KW  - 1.8 V.
KW  - 500 Mbit/s.
KW  - CMOS technology.
KW  - EPR4 channel.
KW  - Shannon limit.
KW  - Add-compare-select recursion architecture.
KW  - Information rate.
KW  - Rate-8/9 convolutional code.
KW  - Register exchange.
KW  - Soft-output Viterbi decoder.
KW  - Survivor-path decoding logic.
KW  - Turbo code.
ER  -