A 500-Mb
Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-μm CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhe...
| में प्रकाशित: | IEEE Journal of solid state circuits 38, 7 (2003). |
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| मुख्य लेखक: | |
| स्वरूप: | लेख |
| भाषा: | English |
| विषय: |