A 500-Mb

A 500-Mb

Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-μm CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhe...

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Vydáno v:IEEE Journal of solid state circuits 38, 7 (2003).
Hlavní autor: Engling Yeo
Médium: Článek
Jazyk:English
Témata:
0.18 micron.
1.8 V.
500 Mbit/s.
CMOS technology.
EPR4 channel.
Shannon limit.
Add-compare-select recursion architecture.
Information rate.
Rate-8/9 convolutional code.
Register exchange.
Soft-output Viterbi decoder.
Survivor-path decoding logic.
Turbo code.