A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS.

A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS.

The design and optimization of a high-speed low-voltage CMOS flash analog-to-digital converter (ADC) are presented. The optimization procedures used during the design give the needed specifications of the different building blocks. Also, an extensive description of the implemented digital error corr...

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Manylion Llyfryddiaeth
Cyhoeddwyd yn:IEEE Journal of solid state circuits 38, 7 (2003).
Prif Awdur: Uyttenhove, K.
Fformat: Erthygl
Iaith:English
Pynciau:
0.25 micron.
1.3 GHz.
1.8 V.
6 bit.
600 mW.
CMOS.
Digital error correction technique.
Flash ADC.
High-speed converter.
Low-voltage converter.
Optimization procedures.
Sampling speed.
Signal-to-noise-plus-distortion ratio.
Total active area.
Total power consumption.