00000cab a22000003a 4500 UP-99796217609277383 Buklod 20231007234122.0 m |o d | ta 100505s xx d | ||r ||||| || DENGII eng Uyttenhove, K. A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS. pp. 1115-1122 The design and optimization of a high-speed low-voltage CMOS flash analog-to-digital converter (ADC) are presented. The optimization procedures used during the design give the needed specifications of the different building blocks. Also, an extensive description of the implemented digital error correction technique is described. The used analog power supply is only 1.8 V. The maximum sampling speed is 1.3 GHz. The signal-to-noise-plus-distortion ratio (SNDR) at 133 kHz is 33.2 dB, and the SNDR at 500 MHz is 32 dB. The total power consumption of the converter at full speed is 600 mW and the total active area is only 0.13 mm2. The ADC is implemented in a 0.25-μm pure digital CMOS technology. 0.25 micron. 1.3 GHz. 1.8 V. 6 bit. 600 mW. CMOS. Digital error correction technique. Flash ADC. High-speed converter. Low-voltage converter. Optimization procedures. Sampling speed. Signal-to-noise-plus-distortion ratio. Total active area. Total power consumption. IEEE Journal of solid state circuits 38, 7 (2003). FO UPD DENG-II Article