00000cab a22000003a 4500 UP-99796217609277382 Buklod 20231007234122.0 m |o d | ta 100505s xx d | ||r ||||| || DENGII eng Gaggl, R. A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-μm CMOS. pp. 1105-1114 A high-resolution multibit sigma-delta analog-to-digital converter (ADC) implemented in a 0.18-μm CMOS technology is introduced. The circuit is targeted for an asymmetrical digital subscriber line (ADSL) central-office (CO) application . An area- and power-efficient realization of a second-order single-loop 3-bit modulator with an oversampling ratio of 96 is presented. The ΣΔ modulator features an 85-dB dynamic range over a 300-kHz signal bandwidth. The measured power consumption of the ADC core is only 15 mW. An innovative biasing circuitry is introduced for the switched-capacitor integrators. 0.18 micron. 15 mW. 3 bit. 300 kHz. ADSL-CO applications. CMOS. Area-efficient realization. Asymmetrical digital subscriber line. Biasing circuitry. Central-office application. Dynamic range. Multibit delta-sigma ADC. Oversampling ratio. Power consumption. Power-efficient realization. Second-order single-loop modulator. Signal bandwidth. Switched-capacitor integrators. IEEE Journal of solid state circuits 38, 7 (2003). FO UPD DENG-II Article