00000cab a22000003a 4500 UP-99796217609277054 Buklod 20231007234120.0 m |o d | ta 100430s xx d | ||r ||||| || DENGII eng Verbauwhede, I. Design and performance testing of a 2.29-GB s Rijndael processor. pp. 569-572 This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mW of power consumption in a 0.18-μm CMOS standard cell technology. This integrated circuit implements the Rijndael encryption algorithm, at any combination of block lengths (128, 192, or 25 bits) and key lengths (128, 192, or 256 bits). We present the chip architecture and discuss the design optimizations. We also present measurement results that were obtained from a set of 14 test samples of this chip. 0.18 micron. 2.29 GB/s. 25 to 256 bit. 56 mW. AES compliant encryption chip. Advanced Encryption Standard. CMOS standard cell technology. Rijndael processor. Block lengths. Chip architecture. Design optimizations. Encryption throughput. Key lengths. Power consumption. Secret key cryptography. IEEE Journal of solid state circuits 38, 3 (2003). FO UPD DENG-II Article