00000cab a22000003a 4500 UP-99796217609277037 Buklod 20231007234120.0 m |o d | ta 100430s xx d | ||r ||||| || DENGII eng Borgatti, M. A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I O. pp. 521-529 A system chip targeting image and voice processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an embedded reconfigurable processor built by joining a configurable and extensible processor core and an SRAM-based embedded field-programmable gate array (FPGA). Application-specific bus-mapped coprocessors and flexible input/output peripherals and interfaces can also be added and dynamically modified by reconfiguring the embedded FPGA. The architecture of the system is discussed as well as the design flows for pre- and post-silicon design and customization. The silicon area required by the system is 20 mm2 in a 0.18-μm CMOS technology. The embedded FPGA accounts for about 40% of the system area. 0.18 micron. CMOS technology. FPGA. SRAM-based embedded field-programmable gate array. Application-specific bus-mapped coprocessors. Customizable I/O. Customization. Design flows. Dynamically extensible embedded microprocessor. Embedded reconfigurable processor. Face-recognition application. Flexible input/output peripherals. Image processing. Multimedia computing. Post-silicon design. Pre-silicon design. Programmable logic. Recognition application domains. Reconfigurable system. Silicon area. System architecture. Voice processing. IEEE Journal of solid state circuits 38, 3 (2003). FO UPD DENG-II Article