A multibit sigma-delta ADC for multimode receivers.

A multibit sigma-delta ADC for multimode receivers.

A 2.7-V sigma-delta modulator with a 6-bit quantizer is fabricated in a 0.18-μm CMOS process. The modulator makes use of noise-shaped dynamic element matching (DEM) and quantizer offset chopping to attain high linearity over a wide bandwidth. The DEM algorithm is implemented in such a way as to mini...

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Vydáno v:IEEE Journal of solid state circuits 38, 3 (2003).
Hlavní autor: Miller, M.R
Médium: Článek
Jazyk:English
Témata:
0.18 micron.
1.92 MHz.
2.7 V.
23 MHz.
30 mW.
46 MHz.
50 mW.
6 bit.
6-bit quantizer.
625 kHz.
Delay minimization.
Direct-conversion cellular receivers.
Direct-conversion radio receiver.
High linearity.
High resolution quantizer.
Mixed-signal integrated circuit.
Modulator feedback loop.
Multibit sigma-delta ADC.
Multibit sigma-delta analog-to-digital converter.
Multimode receivers.
Noise-shaped dynamic element matching.
Power consumption.
Power dissipation.
Quantizer offset chopping.
Sampling frequency.
Signal-to-noise ratio.
Spurious-free dynamic range.
Wide bandwidth.
0.18-μm CMOS process.