Loop-based interconnect modeling and optimization approach for multigigahertz clock network design.

A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including...

詳細記述

書誌詳細
出版年:	IEEE Journal of solid state circuits 38, 3 (2003).
第一著者:	Xuejue Huang
フォーマット:	論文
言語:	English
主題:	Power4 chip. Clock distribution. Clock interconnect simulation efficiency. Closed-form loop resistance models. Design guidelines. Electromagnetic simulations. Fast physical design exploration. Fully shielded global clock interconnect structures. High-frequency effects. Inductance models. Interconnect performance optimization. Loop-based interconnect modeling. Multigigahertz clock network design. Optimization. Proximity effects. Single effective loop RLC chain. Timing analysis.