Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. - Xuejue Huang
A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed.
Keywords: Power4 chip; Clock distribution; Clock interconnect simulation efficiency; Closed-form loop resistance models; Design guidelines; Electromagnetic simulations; Fast physical design exploration; Fully shielded global clock interconnect structures; High-frequency effects; Inductance models; Interconnect performance optimization; Loop-based interconnect modeling; Multigigahertz clock network design; Optimization; Proximity effects; Single effective loop RLC chain; Timing analysis