High-Level Implementation of the 5-Stage Pipelined ARM9TDM Core - Arandilla, Christiensen dela Cruz
Portable devices have increasingly become a necessity for everyday living, as they have revolutionized both data processing and information gathering. However, users continually demand for more processing power from these devices for use in mobile applications. Since portable or mobile devices can only have limited power supply, their processors must have low power consumption and a small die size and at the same time can provide high performance. Thus, the ARM9TDMI, successor of the popular ARM7TDMI microprocessor, was designed to address the current needs of embedded applications. This project is an implementation of a 32-bit RISC processor based on the ARM9TDMI core. Its main features are its use of a 5-stage pipeline consisting of fetch, decode, execute, memory access, and write back stages and a Harvard architecture, which means it has separate data and instruction interfaces. It implements the ARMv4T instruction set architecture that uses both the 32-bit ARM instructions and their corresponding 16-bit Thumb instructions. It includes a high-speed multiplier and debug capabilities using JTAG boundary scan interface. It does not, however, include an EmbeddedICE-RT module. The project was coded using the Verilog Hardware Description Language and was simulated using Synopsys VCS. The verified code was synthesized for logic design optimizations using Synopsys Design Vision using 0.25ľm standard cells. The layout, which was generated by Synopsys Astro, was characterized as exhibiting the following specifications: maximum operating frequency of 35.46 MHz, an average power consumption of 15.72 mW and a chip size of 1.5628 sq. mm.