Implementation of a Least Mean Squares (LMS) based ITU-T G.168 digital network echo canceller on a Xilinx Virtex 5 SXT FPGA - Medina, Keone Karl Apadua
A digital echo canceller is an adaptive signal processor used to replace echo suppressors in today's modern telecommunications network. ITS main function is to eliminate or at least reduce echo, produced by imperfect signal separation at the hybrid in a public switched telephone network (PSTN), to an acceptable level. An effective adaptive filter algorithm dictates the canceller's characteristics like convergence times, residual and returned echo levels and ensures the voice quality in telephone network transmission. This project presented a digital network echo canceller implementation on a Xilinx Wirtex 5 SXT FPGA and partly complies with the requirements stated in the ITU-T G.168 recommendation for digital network echo cancellers. This includes signal processing blocks such as a least mean squares (LMS) - based echo estimator/adaptive filter, ITU-T G.711 pulse code modulation (PCM) codecs, and a nonlinear processor. Different tests were done to ensure that the implemented system complies with the minimum performance requirements stated in the G.168 recommendation.