APA (7th ed.) Citation

Medina, K. K. A. Implementation of a Least Mean Squares (LMS) based ITU-T G.168 digital network echo canceller on a Xilinx Virtex 5 SXT FPGA.

Chicago Style (17th ed.) Citation

Medina, Keone Karl Apadua. Implementation of a Least Mean Squares (LMS) Based ITU-T G.168 Digital Network Echo Canceller on a Xilinx Virtex 5 SXT FPGA. 2009.

MLA (9th ed.) Citation

Medina, Keone Karl Apadua. Implementation of a Least Mean Squares (LMS) Based ITU-T G.168 Digital Network Echo Canceller on a Xilinx Virtex 5 SXT FPGA.