Medina, K. K. A. Implementation of a Least Mean Squares (LMS) based ITU-T G.168 digital network echo canceller on a Xilinx Virtex 5 SXT FPGA.
Lua i Stíl Chicago (17ú heag.)Medina, Keone Karl Apadua. Implementation of a Least Mean Squares (LMS) Based ITU-T G.168 Digital Network Echo Canceller on a Xilinx Virtex 5 SXT FPGA. 2009.
Lua MLA (9ú heag.)Medina, Keone Karl Apadua. Implementation of a Least Mean Squares (LMS) Based ITU-T G.168 Digital Network Echo Canceller on a Xilinx Virtex 5 SXT FPGA.
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