Design and implementation of integrators using operational transconductance amplifiers in a 90nm CMOS process - Prado, Alvin Osorio
Analog to Digital Converters (ADC) are widely used in communications, instrumentation control, and signal processing. The delta-sigma architecture offers high resolution, low cost and low power benefits at the cost of speed. It is composed of an analog modulator block, which consist of an integrator, a compactor and a one-bit digital-to-analog converter, and a signal filter block. The integrator plays a vital role in the performance of a delta-sigma ADc, as it performs noise-shaping, attenuates noise in the signal band, and sets the bandwidth of the entire modulator. The goal of this project is to design four integrators implemented in a standard 90nm CMOS technology. These integrators are implemented using folded cascode operational transconductance amplifiers. The integrator configuration employed are: single-ended continuous time, single-ended discrete time, fully-differential continuous time, and fully-differential discrete time. The specifications are DC gain, unity gain frequency, phase margin, and slew rate. Schematic and extracted results for the single-ended and fully differential OTAs were able to attain differential mode DC gains greater than 55dB and slew rates greater than 113V/usec. The designated OTAs consume less than 19uW of power. The continuous time integrators were able to attain a unity gain frequency greater than 24MHz at a phase margin of 88 degrees. The discrete-time integrators were able to attain a unity gain frequency greater than 24MHz at a phase margin of 59 degrees. The fully -differential discrete-time integrator was found to be most appropriate for the ADC because of better common-mode and power supply rejection; and improved gain stability and frequency response due to feedback, over the other integrator configurations.