Cita APA (7a ed.)

Alidio, L., Fernandez, J. L., Montes, J. A. G., & Palma, C. M. J. Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache.

Cita Chicago Style (17a ed.)

Alidio, Lianne, Jose Luis Fernandez, Julie Ann Gaspara Montes, y Camille Mary Joyce Palma. Implementation of a 32-bit Dual Core ARM7 Microprocessor with Split-private Level One Cache and Shared Level Two Data Cache. 2009.

Cita MLA (9a ed.)

Alidio, Lianne, et al. Implementation of a 32-bit Dual Core ARM7 Microprocessor with Split-private Level One Cache and Shared Level Two Data Cache.