Iterative decoder architectures.

Implementation constraints on iterative decoders applying message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the decoding alg...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	IEEE Communications magazine 41, 8 (2003).
1. Verfasser:	Yeo, Engling
Format:	Artikel
Sprache:	English
Schlagworte:	VLSI implementation. Bit error rate performance. Communications receivers. Decoding algorithm. Implementation constraints. Iterative decoder architectures. Low-density parity check codes. Message-passing algorithms. Parallelism. Serial implementations. Signal-to-noise ratio turbo codes.