00000cab a22000003a 4500 UP-99796217608899891 Buklod 20231007234007.0 m |o d | ta 090630s xx d | ||r ||||| || DENGII eng Yeo, Engling Iterative decoder architectures. pp. 132-140 Implementation constraints on iterative decoders applying message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the decoding algorithm. Turbo codes and low-density parity check codes, in particular, are evaluated in terms of their suitability for VLSI implementation in addition to their bit error rate performance as a function of signal-to-noise ratio. It is necessary to consider efficient realizations of iterative decoders when area, power, and throughput of the decoding implementation are constrained by practical design issues of communications receivers. VLSI implementation. Bit error rate performance. Communications receivers. Decoding algorithm. Implementation constraints. Iterative decoder architectures. Low-density parity check codes. Message-passing algorithms. Parallelism. Serial implementations. Signal-to-noise ratio turbo codes. IEEE Communications magazine 41, 8 (2003). FO UPD DENG-II Article