Iterative decoder architectures.

Iterative decoder architectures.

Implementation constraints on iterative decoders applying message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the decoding alg...

Fuld beskrivelse

Bibliografiske detaljer
Udgivet i:IEEE Communications magazine 41, 8 (2003).
Hovedforfatter: Yeo, Engling
Format: Article
Sprog:English
Fag:
VLSI implementation.
Bit error rate performance.
Communications receivers.
Decoding algorithm.
Implementation constraints.
Iterative decoder architectures.
Low-density parity check codes.
Message-passing algorithms.
Parallelism.
Serial implementations.
Signal-to-noise ratio turbo codes.