Iterative decoder architectures.

Iterative decoder architectures.

Implementation constraints on iterative decoders applying message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the decoding alg...

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Manylion Llyfryddiaeth
Cyhoeddwyd yn:IEEE Communications magazine 41, 8 (2003).
Prif Awdur: Yeo, Engling
Fformat: Erthygl
Iaith:English
Pynciau:
VLSI implementation.
Bit error rate performance.
Communications receivers.
Decoding algorithm.
Implementation constraints.
Iterative decoder architectures.
Low-density parity check codes.
Message-passing algorithms.
Parallelism.
Serial implementations.
Signal-to-noise ratio turbo codes.