Iterative decoder architectures.
Implementation constraints on iterative decoders applying message-passing algorithms are investigated. Serial implementations similar to traditional microprocessor datapaths are compared against architectures with multiple processing elements that exploit the inherent parallelism in the decoding alg...
| में प्रकाशित: | IEEE Communications magazine 41, 8 (2003). |
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| मुख्य लेखक: | |
| स्वरूप: | लेख |
| भाषा: | English |
| विषय: |