Gigabit Ethernet switches using a shared buffer architecture.

Gigabit Ethernet switches using a shared buffer architecture.

Gigabit Ethernet networks have seen great demand in recent years. This growth was fueled by both an increase in port speed at the client side and new applications in MAN and WAN space. In this article, we report a highly integrated Ethernet switch IC design that supports 12 gigabit ports and one 10...

Täydet tiedot

Bibliografiset tiedot
Julkaisussa:IEEE Communications magazine 41, 12 (2003).
Päätekijä: Lau, M.V
Aineistotyyppi: Artikkeli
Kieli:English
Aiheet:
0.18 micron.
10 Gbit/s.
CMOS.
Ethernet interface.
WAN space.
Custom mixed-signal circuits.
Flexible policy engine.
Gigabit Ethernet switches.
Integrated Ethernet switch IC design.
Packet filtering.
Parallel memory access.
Pipelined structure.
Search memory.
Shared buffer architecture.
Switching performance.
Tail buffer architecture.
Variable packet length.
Wirespeed search performance.