00000cab a22000003a 4500 UP-99796217608899851 Buklod 20231007234007.0 m |o d | ta 090630s xx d | ||r ||||| || DENGII eng Lau, M.V. Gigabit Ethernet switches using a shared buffer architecture. pp. 76-84 Gigabit Ethernet networks have seen great demand in recent years. This growth was fueled by both an increase in port speed at the client side and new applications in MAN and WAN space. In this article, we report a highly integrated Ethernet switch IC design that supports 12 gigabit ports and one 10 Gb port. All packet memory and search memory are integrated on chip. A deeply pipelined structure with parallel memory access is employed to achieve wirespeed search performance. A flexible policy engine is designed to allow packet filtering and modification. A novel tail buffer architecture is proposed to address the variable packet length issue in the shared buffer architecture. Custom mixed-signal circuits are incorporated to implement the 10G Ethernet interface in XGMII. The chip integrates 70 million transistors in a 16 mm × 15 mm die using 0.18 μm CMOS technology. The chip has been tested to verify the wirespeed searching and switching performance. 0.18 micron. 10 Gbit/s. CMOS. Ethernet interface. WAN space. Custom mixed-signal circuits. Flexible policy engine. Gigabit Ethernet switches. Integrated Ethernet switch IC design. Packet filtering. Parallel memory access. Pipelined structure. Search memory. Shared buffer architecture. Switching performance. Tail buffer architecture. Variable packet length. Wirespeed search performance. IEEE Communications magazine 41, 12 (2003). FO UPD DENG-II Article