A combined input and output queued packet switched system based on PRIZMA switch on a chip technology.

A packet-switched system architecture based on the combination of a single-chip output-buffered switch element and input queues that sort arriving packets on a per-output-port basis is proposed. Scheduling is performed in a distributed two-stage approach. Independent arbiters at each of the inputs r...

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Bibliographic Details
Published in:	IEEE Communications magazine 38, 12 (2000).
Main Author:	Minkenberg, C.
Format:	Article
Language:	English
Subjects:	PRIZMA switch. Arbiters. Bursty traffic. Chip technology. Distributed two-stage scheduling. High-throughput implementation. Input contention resolution. Input queues. Input-output queued packet switched system. Output contention resolution. Output-buffered switch element. Packet-switched system architecture. Port speed. Quality-of-service mechanisms. Shared-memory switch. Simulation results. Single-chip output-buffered switch element.