An asynchronous implementation of a 32-bit DLX microprocessor - Dumaguing, Christian Loyd G.
Synchronous designs have grown dominant in terms of implementing digital systems because of their simpler design and well established design methodologies. However, using a global clock poses several disadvantages. These disadvantages give large-scale designers challenging problems, of which include: clock skews, high power consumption and electro-magnetic noise. Asynchronous implementations provide solutions to these problems. In this research, a fully asynchronous 32-bit DLX microprocessor is implemented using the HDL (hardware design language) design flow. The architecture of this system uses an asynchronous pipeline of registers. Sutherland's control circuit for micropipelines is incorporated to handle the handshaking between the stages of the pipeline. The pipeline stages of the BaseDLX, previously implemented at the Intel Microprocessor Laboratory (UP-IML) is adopted. By using the micropipeline concept, additional timing circuitries are added to facilitate the diverse triggering of the asynchronous modules. Post-synthesis characteristics of the final system show a 189.88% increase in the execution time as compared with the Base DLX's performance. This slowdown is attributed to the return to zero property of the four phase handshaking protocol used in the system. An increase of 15.24% in the area from the Base and 4.22% from the GALS DLX, also another project from the UP-IML, is observed and credits from the unoptimized modules of the asynchronous control circuit. Lastly, a 19.81% decrease in total power consumption is observed on the Asynchronous DLX as compared to that of the Base DLX.