Design and performance of a threshold-based load balancing scheme in an ATM switch.
We consider an ATM switch consisting of a number of output buffered ATM switch elements operating in paralle. Such an architecture may lead to uneven distribution of cells over the parallel switch element buffers, if no modifications
| 出版年: | Computer networks and ISDN systems. 29, 2 (1997). |
|---|---|
| 第一著者: | |
| フォーマット: | 論文 |
| 言語: | English |
| 主題: |