00000ctm a22000003a 4500 UP-99796217608650636 Buklod 20090108113416.0 m |o d | ta 090108s xx d r |||| u| (iLib)UPD-00071596426 DENGII eng LG 993.5 2008 E64 L86 Luna, Anne Lorraine S. Implementation of the complete ARM7TDMI-S instruction set on a debug-capable core Anne Lorraine Sadueste Luna, Christina Marianne Gervasio Mantaring, Maria Patricia Rouelli Garcia Sabino. 2008. ix, 155 leaves ill. + 1 computer laser optical disc (4 3/4 in.) Undergraduate Student Project (B.S. CoE)--University of the Philippines, Diliman. In this day and age, portable and embedded systems continue to permeate almost all aspects of everyday life. Thus, there is a premium placed on microprocessors with low power consumption, small footprints, and good code density. Moreover, because these microprocessors are deeply entrenched into the system, accessing their cores poses another challenge, thereby increasing the demand for debug-capability. This document presents the implementation of a processor that is based on the ARM7TDMI-S, which is the synthesizable version of the most widely used 32-bit RISC microprocessor in the industry today. It uses the ARMv4T instruction set, which includes both 32-bit ARM instructions and their shorter 16-bit Thumb versions. The instruction set implementation is supported by advanced hardware, which includes an enhanced multiplier and extended debug capabilities through a JTAG test access port. It does not, however, include an EmbeddedICE-RT module. The project was coded using Verilog HDL, simulated using Synopsys, and synthesized using 0.25-micrometer standard cells. Its layout, generated by Synopsys Astro, has a maximum operating frequency of 26.3 MHz, a chip size of 0.9389 sq. mm and and average power consumption of 9.30mW. Microprocessors Design and construction. RISC microprocessors. ARM7TDMI-S. Mantaring, Christina Marianne G. Sabino, Maria Patricia Rouelli G. FI Thesis UPD DENG-II LG 993.5 2008 E64 L86 Thesis