DLXPlus a DLX processor simulator with memory subsystem - Diaz, Michelle A.
Simulators for processors often disregard the significance of simulating the memory subsystem. Performance-wise, the memory subsystem, primarily the cache, plays a vital part. It affects the speed of execution of instructions being processed by the processor. The time to access the memory subsystem depends on several factors such as the cache hit rate, the cache capacity, write and replacement policies, and type of associativity. This gives rise to the need to include the memory subsystem in a simulator as well. DLXPlus simulator aims to support the simulation of a 32-bit DLX microprocessor with a configurable level-1 split cache. This simulator displays and summarizes the execution of instructions in a DLX five-stage pipeline. It shows the cache and processor performance statistics, which are essential in evaluating the performance of different programs. Furthermore, DLXPlus simulator generates memory trace file, which can be useful for future projects involving memory subsystem simulation.