00000ctm a22000003a 4500 UP-99796217608650500 Buklod 20090106162851.0 m |o d | ta 090106s xx d r |||| u| (iLib)UPD-00071596271 DENGII eng LG 993.5 2008 E64 D487 Dela Cruz, Sherlyn Caubalejo Design and implementation of operational amplifiers with programmable characteristics in a 90nm CMOS Process Sherlyn Caubalejo dela Cruz, Mark Gerard Trinos delos Reyes, Terence Co Gaffud. 2008. xvi, various paging col. ill. + 1 computer laser optical disc (4 3/4 in.) Undergraduate Student Project (B.S. ECE)--University of the Philippines, Diliman. Operational amplifiers (op-amps) serve as the basic building blocks in almost every analog and mixed-signal electronics circuits such as analog-to-digital converters (ACD's), digital-to-analog converters (DAC's), filters, and even switched-capacitor circuits. One of the most common problems in op-amp design is the variation in the op-amp's performance caused by process variations during fabrication. In this project, a procedure on integrating programmable bias networks into an operational amplifier is developed. The programmable network driven by digital input words makes the output bias currents and voltages variable, thus making the op-amp tunable for proper operation even after chip fabrication. Furthermore, the programmability of other op-amp parameters such as gain, slew rate, and compensation are explored to increase the capability and flexibility of the op-amp. The programmability schemes are employed on two base op-amp topologies namely, the Two-stage Miller and the Folded Cascode. Results for the Two-stage Miller op-amp are able to attain a differential voltage gain greater than 50 dB and a gain-bandwidth product of 1 GHz. The final design of the 4-bit Programmable Bias blocks attained a range of 8μ A to 12μA. The 4-bit Programmable Gain amplifier attained a range of 0 to 17 dB. The 4-bit Programmable Slew Rate attained a range of 504 V/μs to 895 V/μs for the integration with the Miller op-amp and 434 V/μs to 1,354 V/μs for the integration with the Folded Cascode. And lastly, the Programmable Compensation was able to increase the phase margin from 35.8° to 61.2 ° and from 0° to 75.31° for the integration with the Two-stage op-amp and Folded Cascode op-amp respectively. This study on programmable op-amps implemented in the 90nm CMOS process is the first to be undertaken in the Microprocessors Laboratory of the EEE Department and succeeded in providing a starting ground for possible future studies relate to this field. Operational amplifiers. Metal oxide semiconductors, Complementary. Operational amplifiers Design and construction. CMOS process. Folded Cascode. Delos Reyes, Mark Gerard Trinos. Gaffud, Terence Co. FI Thesis UPD DENG-II LG 993.5 2008 E64 D487 Thesis