Implementation of a 32-bit dual core ARM7 microprocessor with single level cache - Castro, Janelle Legaspi
Shared-memory multiprocessors have become a cost-effective way of providing increased computing power and speed, mainly because they utilize low-cost microprocessors interconnected with shared memory modules. However, memory access tends to become a performance bottleneck due to multiple processors contending for the shared memory resource. An efficient way of reducing memory traffic for each processor is to include a cache memory. Its locality of memory references allows caches to perform majority of the memory requests. Therefore it is the project's objective to develop a dual-core ARM7 microprocessor with a single-level cache to improve the performance of the recent ARM7 Core implementations. The previous cache implementation for a dual-core system used a unified cache architecture, whereas for this project, a split-cache architecture was implemented. Each processor has its own L1 cache, split into data and instruction caches. A snoop control unit is added to resolve data coherence and memory consistency problems arising from the split-cache implementation. To manage simultaneous memory accesses of the two ARM7 cores, a bus arbitration unit was also included. The project is designed and implemented targeting 0.25μm CMOS standard cells, using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The design is tested for functionality. The ARM 4CE Base Core was simulated to determine the effect of the enhancement of the arithmetic blocks. The maximum operating clock frequency obtained was 22.7MHz, and the core area recorded was 0.6503 mm². The average power consumed by the ARM 4CE Base Core was found out to be 10.3352 mW. The observed minimum power was 5.234 mW, and the observed maximum power was 11.683 mW. The addition of a cache memory subsystem decreased the number of execution cycles of the ARM 4CE, thus improving its execution time. The improvement due to the cache insertion comes at the expense of higher area utilization and increase in power consumption. The area of the ARM 4CE with Cache is 24 times larger and its power consumption is 48 times more compared to the ARM 4CE Base Core alone. The Dual Core ARM 4CE with Cache improved the throughput of the system. The two cores were able to execute a parallelized program through thread scheduling by the use of atomic instructions.