GALS DLX design and implementation of a semi-asynchronous DLX microprocessor - Canoza, Ralph Riley D.
Synchronous system designs have well-developed design methodologies. However, as systems grow larger and more complex, problems, such as clock skew, become a major concern. That is why some researches gained interest in asynchronous systems. Aside from eliminating the problem of clock skew in synchronous processors, it also delivers average-case performance instead of worst-case. Low power dissipation is also expected of asynchronous systems because only active modules consume power. Despite the benefits of asynchronous systems, synchronous processors still dominate because asynchronous processors are relatively more difficult to design. Computer-Aided Design (CAD) Tools for asynchronous systems are also very limited and cannot level off with existing synchronous tools. In order to achieve the benefits of both synchronous and asynchronous systems, a semi-asynchronous system can be employed. Globally Asynchronous Locally Synchronous (GALS) system uses synchronous and asynchronous modules to mimic a fully asynchronous system with much less complexity. In this research, the Base DLX microprocessor, implemented at the Intel Microprocessors Laboratory, was modified to fit the GALS system. The Instruction Decode and Execution stages, specifically the Register File and Arithmetic Logic Unit (ALU), were made asynchronous. The remaining synchronous modules were interfaced to the asynchronous parts using an Asynchronous Wrapper to make it seem like a completely asynchronous module to the system. A pausible clock was used for synchronization of signals. All of the blocks were synthesized and tested for functionality. Thus, an approximate synthesized area and delay of the blocks were extracted. The comparison with the BASE DLX resulted to about 31.9% decrease in area mainly because of the use of latches instead of registers. The blocks were also integrated per stage and were tested to be functional. However, the implementation was incompletely verified when the whole system was integrated because of the difference in timing of the blocks. A general handshaking block for all the stages instead of a handshake block for each pipeline can be use to synchronize the timing of the blocks.