FPGA implementation of space-time trellis decoder - Calayag, Marciano Jr. S.
Space-Time Trellis Codes (STTC) encoding and decoding require a higher level of complexity than Space-time Block Codes (STBC) but unlike STBC which provides only diversity gain, STTC provides both diversity gain and coding gain. In this project, a space-time trellis encoder and decoder was implemented in a single Field Programmable Gate Array (FPGA). For the encoder, modifications were made to the design by Fadera, et. al, in a previous Digital Signal Processing Laboratory (DSP Lab) project, FPGA Implementation of Space-Time Encoders. The Memec Virtex-4 FX12 LC development kit utilizing the Xilinx XC4VFX12-10FF668C FPGA will be used. The decoding process uses Maximum Likelihood Detection through the Viterbi Algorithm. Xilinx ISE and Chipscope Pro were used to simulate the code of the STT encoder and decoder. The input bits to the encoder will be compared to the output bits of the design decoder.