A study of different encoding techniques applied on high-capacitance buses for low-power processor design - Realo, Alberto Bismonte (2004)
In this thesis, the effectiveness of applying 10 different bus-encoding techniques to lower the power consumption of processors is investigated. A standard cell based design methodology was followed in the implementation of the encoder and decoder circuits. The bus lines targeted are the instruction and data address bus lines in the communication of the processor and the on-chip cache or memory. The effect of each bus encoding technique on the processors' switching activity, power consumption, performance, and area are measured. To quantify the effectiveness of each technique, the minimum value of bus capacitance that will result in power saving are determined. Simulation and measurement results of three testbenches are also compared and analyzed to identify the most effective technique suited for instruction address or data address buses. It was established that most of the encoding techniques studies is able to provide significant savings of up to 50% switching reduction, and up to 20% in total power consumption.
Thesis (M.S. Electrical Engineering : Microelectronics Option)--University of the Philippines, Diliman.
Keywords: Microcomputers -- Buses; Capacitance meters -- Design and construction; Electric capacity